Metal Resistors – Your Unexpected Friend In Wire Management

Yes, you read the title right. If you haven’t seen or used metal resistors (a.k.a. metres, rm, etc.) in your schematics, I hope this post opens a new door. Most modern PDKs already include metal resistor cells in the library. If not, you could create your own with CAD team’s help (if you have access to one). Normally, we work hard to avoid metres because they show up uninvited and mess up everything after extraction. However, they can be extremely helpful when placed properly, especially for simulation, testing and documentation purposes. In this post, I will explain in more details how to effectively utilize metres in these areas.

Some wires deserve a name

Metal resistors have been around for a long time. I only began using them more heavily when finFETs came about. As explained in another post, layout and parasitics are now dominant factors in a design’s success. Therefore, many routing wires need to be scrutinized just like devices, and they deserve to have dedicated cells.

The easy example we can all agree on is on-chip inductors. Although many PDKs come equipped with inductor pcells, we probably still end up drawing our own. There are many methods to deal with inductor LVS (black boxing, creating pcell, etc.), but my current favorite is to use metal resistors. These schematics are boring to say the least (the resistance is negligible, often <<1Ohm and essentially a short), but they will pass LVS as is without any funky setups. To simulate, you replace it with another schematic view generated from your favorite EM solver, be it an inductor model or nport model. The possibilities are endless: a similar schematic can apply to transmission lines as another example.

Perhaps my favorite use case is for creating a standalone routing cell for a critical net. This happens the most when a signal need to branch out and reach multiple destinations. Metal resistors can help define this design intent early on (especially if you have already experimented with the floorplan). This is just another aspect of the “draw it like you see it” mentality. The example shown below is for a simple clock route, but you can easily expand this to be a distributed or tree structure. Note that the schematic could be “less boring” now that I added some parasitic capacitors to both supply and ground.

Let’s compare the two schematics below. On the top is a straightforward one showing a clock buffer driving the signal to the top and bottom buffers. Although not drawn here, one can imagine an improved version including annotated routing information and a cartoon floorplan in the corner. So how can we further improve upon that? That’s where the bottom schematic come in with a routing cell created with metal resistors.

Here are some of the biggest benefits of the bottom schematic:

1. It forces you to treat routing plans seriously and acknowledge that it’s part of your design. Heck, it makes everyone who looks at this say that routing cell must be very important.
2. There are two more unique and critical nodes (i.e. clk_top & clk_bot) for easy probing during simulation. There might be some who are fluent in netlist and know exactly where the signal of interest is, but that’s not me. With this schematic I can easily probe these two nodes and obtain useful information right away (e.g. delay matching).
3. This schematic intrinsically separates the design problem into two parts: driver fan-out sizing and parasitics. So if the post layout simulation results weren’t as desired, we could have a better plan of attack for debug. Is it routing parasitics or fanout limited? Maybe I should try C-only extraction for the routing cell to see if it’s resistance dominant. Maybe there is some layout issue in the buffer instead of the wire routes, so let’s use extracted view only for the routing cell. I hope that you see this is a more efficient scheme to help designers isolate layout issues.
4. Let’s talk about the supply/ground pins. The obvious reason is give the extracted capacitors a better reference rather than “0”. The more important reason is that these pins will remind you to include power grids surrounding the wires in layout. Many designers find out much later that top level integration slapped a dense power grid over their critical signals. This can lead to yelling, hair pulling and sometimes redesign. Putting power pins on routing cells lower the chance of such “surprises”.

Despite the examples focusing on high speed wires, metal resistors could be equally important for lower speed applications. When resistance matching is critical (e.g. summing node for a current DAC), segmenting a net with metal resistors can work wonders.

On-chip probe points

Now let’s go to other extreme of the speed spectrum: DC test voltages. For the uninitiated, real world designs often require the ability to measure critical on-chip signals. For digital blocks, an internal mux and a protocol of your choice (I2C, SPI, monitor bus, etc.) is sufficient to select and send signals off chip. The principle is the same for analog signals, except you have to decide the exact locations to probe in the physical layout.

There are mainly two categories of test signals: performance critical and location critical. Performance critical signals are ones that you don’t wish to disturb when you look at them. For example, you don’t wish to add extra capacitive loading on a high speed net or you want to make sure no extra noise can be injected into the VCO control voltage through the test path. The typical solution is to use a large isolation resistor (could be ~100k) locally before sending the voltage to a far-away analog mux. In this case, the resistor is an actual device like a poly resistor.

In other cases, extra loading is not problematic but you are specific about the location and metal layer where the signal is probed. Supply and ground network is the best example for this use. Our friendly metal resistor can be the perfect fit here. My suggestion is to create a corner in the schematic that summarizes the probe signals and their respective metals like below. This little corner provides layout engineers enough initial information (fine tuning is certainly required), and also serves as documentation.

To those who are pcell savvy or wish to improve upon this, you can create a wrapper cell with custom symbols with metal information written on them. The size can also be adjusted for more compact drawings (schematic real estate is valuable too). Depending on your appetite and the scale of your design, this might be an overkill. However, there is a similar use case in the digital land that might make more sense for some.

Digital mapper

Let’s take the diagram above and flip it left and right. Then, you have a bus coming in on the left, and branched out to new unique pins on the right. Remember the configuration section of the symbol here? This list can grow quickly for a larger block, and propagating all these pins to higher level could become troublesome. Somewhere in the schematic hierarchy one needs to connect these meaningfully named pins to the dull digital buses. Perhaps you have seen something like this before

Ah, the good old connect by net name crime. The noConn cells are there to eliminate the warnings due to a few unused bits, but now the whole bus is “not connected”. There is no structure in how the digital bits are connected to their destinations. No amount of “dynamic net highlighting” is gonna save your eyes when you need to debug a wrong connection. Your layout partner is probably also making a voodoo doll and sharpening some needles. Introducing the digital mapper cell, sponsored by metal resistors

The magic happens inside the mapper like below. Luckily, tools today recognize buses that are tapped off from a bigger bus without complaining. This results in a much cleaner look for the schematic and nothing is connected by net name. Right away, it conveys more information about each bit’s usage, expected metal layer and even relative locations in the layout. For example, the noConns signify routing tracks reserved for shielding around critical signals, like power down and reset.

Building upon this unit metres mapper group, a complete mapper cell can contain much more information about the circuit’s programmability. You guessed it – here can be go-to place for all the default values if you annotate them down. What’s better is you could see which configurations share the same register map address. You can even read off the combined value in hex for digital and verification folks. This is just another example of schematic as documentation, made possible by metal resistors. From layout’s point of view, the initial effort might be similar, but any incremental change becomes easier to track with this cell.

I have one final note about the digital mapper cell. Depending on your team’s own methodology, the mapper inputs could potentially be lumped into a single wider bus. This can help simplify the symbol of a mid-level block and makes higher level schematics easier to read and draw. But again, it’s up to your personal taste.

Dear Santa

As a build up to my personal wish list, here is a my bad attempt at a Christmas poem:

‘Twas the night before Christmas when an unexpected friend showed up in the PDK,

Her name was Metres, who smiled and said “your wires are going to be OK”.

Forgive me Santa for being so greedy,

but I still wish Metres can be a bit more handy.

Don’t you know a special elf named CAD?

Perhaps he can help, I heard he’s a good lad.

I know he is busy all season long,

but here is the list for what I want

1. As mentioned above, the metres symbols should display metal layer info directly.
2. Currently, pins can be assigned a “type” (power, signal, analog, etc.), but I personally never used them and understood their purpose. Is it possible to create a “digital” pin type and give me a field to input “default values”? It would be nice if the default value can show up in the symbol pin automatically.
3. Is it possible to read in a digital mapper cell and generate a spreadsheet for the configuration table? This probably requires #2 to happen first.
4. To expand upon #3, perhaps the process of creating configuration spreadsheets can be fully automated if special metres are recognized when tracing an entire netlist. Now designers only need to make sure their schematics contain the configuration details, and never have to touch Excel.
5. A similar methodology might also work for analog test signals, just need another special flavor of metres pcell.

These might still be pipe dreams, but dreams do come true if we wish hard enough. The bigger point, however, is that we need to keep thinking about ways to enhance productivity, improve design scalability and reduce chances of error. An effective use of a tiny element like metres can translate to huge gain in efficiency. You never know what would be the next gem you find or create in the PDK.