Category: Crash course

When we hear “system” in IC design, normally two types pop in our heads – the billion(or trillion!)-transistor chips or the PCBs that host these SoCs. To be completely honest, I never really liked the term “SoC”. It forces us to think a system must have a processor, memory, a plethora of I/Os and much more to be worthy of this name. In reality, every component inside an “SoC” is a system by itself with many interconnected sub-blocks. This is even more so in the advanced CMOS era where mixed-signal processing and system-level co-optimization is crucial, even for a simple amplifier.

System thinking has never been an emphasis in analog design curriculums (granted there is just too much to cover). However, this causes designers to be often stuck in a weird place. They sometimes aren’t sure how the requirements come about or how their blocks fit in the system, . And yet, we have all witnessed the huge benefits when a designer understands signal processing and system concepts.

The modern digital-assisted analog or analog-assisted digital paradigms call for more designers who can think deeper about the incoming signals, block interfaces and architectures. These are what I believe to be the top 3 pillars in system thinking for analog designers, which we shall explore in more details in this post series.

The 3 pillars of system thinking

You can start practicing designing with a system mindset by asking the following 3 questions (and some sub-questions)

1. Do I understand the nature of the signal coming into my block?
   1. Which signal characteristic is the most important?
   2. What is the worst case signal that I need to handle?
   3. Any signal characteristics that my circuit might be able to exploit?
2. Do I understand my block‘s interface?
   1. Should I use an analog or digital output interface?
   2. Is my load really a resistor or capacitor?
   3. What does my block look like to others?
3. Do I have the right number of loops?
   1. Should I use sizing or loops?
   2. Too few or too many loops?
   3. Does any loops interfere with any important signal characteristics?

The objective here is to develop a habit of challenging the architecture and circuit requirements, even if we are just “humble block designers”. Let’s dive deeper into the first two questions here (architecture and feedback deserves a post by itself) and learn about some of the key concepts and tools at our disposal.

What am I processing?

One of the first things we are taught was the Nyquist-Shannon sampling theorem. Analog designers have this “2x curse” in the back of our heads – somehow we always need to squeeze out twice the signal bandwidth in the frequency domain. Another trap we tend to fall into is ignoring the lower frequencies (also partly due to the 2x curse). The reality is that increasingly more applications and architectures simply don’t follow Nyquist sampling anymore.

For example, modern wireline links operate on baud-rate sampling. Sub-Nyquist sampling is paramount in some software-defined radios (SDR) and other compressive sensing applications. What enables these architectures is the understanding the difference between signal and information bandwidths. The goal of our analog circuitry has always been to preserve or condition the information contained in the signal. Reconstructing the entire signal waveform(i.e. Nyquist sampling) is just a super set of preserving information.

We should begin viewing our signal conditioning blocks all as Analog-to-Information Converter (AIC), a concept inspired by compressed sensing theory. I believe most of the problems can be reframed in the AIC context. In my own field of wired/optical communication, the overall channel’s inter-symbol interference (ISI), which in the conventional sense is bad for signal bandwidth, actually contains valuable information. A maximum-likelihood sequence estimator (MLSE) desires the right amount of ISI for the decoding algorithm to work.

Getting to know your signal?

I encourage all analog designers to grasp what information their circuits are trying to process first. Below are somethings to ask about the signal characteristics that impact the incoming information

1. Is the information carried in a broadband (e.g. wireline) or narrowband (e.g. wireless) signal?
2. Is there a huge discrepancy between the signal bandwidth and the information bandwidth? (e.g. we only care about the long delay times between very sharp periodic pulses, like ECG signal)
3. Is the information in the signal levels, signal transitions, or both? (e.g. level encoded like PAM vs edge encoded like Manchester code)
4. Is there any low frequency or even DC information? (e.g. any encoding on the signal that impact low frequency content?)
5. Is the signal/information arriving continuous or sparsely? (e.g. continuous vs. burst mode)

A fun interview question

The discussion above might sound too high-level or even philosophical to some, so let me give an interview question type example (derived from a real world problem). Let’s say we have a transmit signal that looks like a “train of clocks” as shown below. The signal swing is relatively small and rides on a DC bias on the PCB. A huge DC blocking cap is used on board because the DC bias level is unknown. Your task is to design a receiver circuit for this clock train and preserve the clock duty cycle as much as possible.

The challenge here is a combination of the signal’s burst nature and the board level AC coupling. As a result, the chip’s input signal will have baseline wander, which is always a nuisance.

Our first attempt might be to use a comparator directly. The issue becomes how to set the reference voltage. There is no one reference voltage that can preserve the clock duty cycle for every pulse. The next natural thought is to google all baseline wander techniques out there to see if we can negate the AC coupling completely (then pull my hair out and cry myself to sleep).

Now, if we realize that the information in the clock actually lies in the edges and not the levels, there can be other possibilities. If the edges are extracted and a spike train is created like below, the new receiving circuit might be able to restore the levels from the spikes.

The simplest edge extraction circuit is actually just another AC coupling network, but the cutoff frequency needs to be high enough relative to the clock frequency. A level restorer could be conceptually a pulse triggered latch (w/ the right dosage of positive feedback). Congratulations, we just practiced Analog-to-Information conversion (high-passing to extract edges) and reconstruction (level restoration) and created a much simpler and more robust solution. In fact, the receiver would work equally well if the burst signal is PRBS like.

Exploit signal nature

System thinking in analog design often requires “thinking outside the box” and leads to “easier” solutions. The first step is to understand the information that we aim to process and pinpoint what we could exploit. Like the example above, we took advantage of the fact that the same information lies in the signal transitions as the levels. This led to a solution better suited for this particular application. While we should be proud of making complicated circuits work, we should take equal pride in simpler solutions born from a better understanding of the incoming signal.

What am I driving?

After figuring out what’s coming into our blocks, we now shift the focus to where the output signal is going, or more precisely block interfaces. One major source of frustration is when you tweak a block to perfection but trouble arises when plugged into the system. Either the load doesn’t behave as expected or your own block is the problematic load.

Perhaps everyone can relate to the cringe when seeing heavily Figure of Merit (FOM) engineered publications. Some new circuits are extremely power efficient provided that the input source is a $10,000 box with a wall plug. Needless to say, it’s important to fully understand our blocks’ interface so that we can design and simulate accordingly.

The impedance lies

There aren’t that many lies greater than “my block looks like/drives a pure resistor or capacitor”. While a block’s input or load impedance might look like a pure resistor/capacitor at certain frequencies, every realistic element has a frequency dependent impedance (Exhibit A). Overly relying on simplified R/C loads is another reason why sometimes we can’t trust frequency domain simulations too much.

My readers already know my love for inverters, so let’s take a look at the picture below. As a start, let’s say our circuit is driving an ideal inverter. There shouldn’t be any objection to say the input impedance looks like a capacitor. Fair enough.

Now let’s add a Miller capacitor in there. Right away, things become more complicated than meets the eye. In the case of a small Miller cap relative to the input cap, the Miller cap gets amplified by the inverter gain and one might approximate the input impedance still as a capacitor with a Miller multiplied component. However, if the Miller cap is big enough such that it begins to act as an AC short sooner, the load impedance now behaves as a resistive component because the inverter becomes diode connected (this is also intuition behind pole splitting in Miller compensation).

To be the lord of chaos, I will now throw in a LC-tank at the inverter’s output, and why not cascade another stage (and another and another). Have you lost track of what the input impedance should be yet? Don’t believe this is a real circuit? Here is the resonant clock distribution circuit for a 224Gb/s transmitter. I would feel very uneasy to use simple load capacitors when designing any intermediate stages.

Impedance modeling using nport

The habit of resorting to simple RC loads is not unjustified. They could certainly provide order-of-magnitude results and speed up simulations. However, as illustrated above, that doesn’t guarantee the block would act the same when plugged into a real system. As designers, we need to recognize this possible culprit and address it early on.

We don’t need to look far to see a better way to model our block interfaces. Signal and power integrity (SI/PI) experts have long figured out that every trace on a PCB is an n-port network.

We often forget the first thing we learned. Electronics 101 has prepared us for n-port modeling with Thevenin/Norton equivalent networks, and even a MOS transistor’s small signal model is network based. And yet, we rarely think about our own circuits as a network and having S-parameters. For some reason, S-parameters are synonymous with RF designs, but in reality there is mathematical equivalence between S-parameters and Y/Z parameters, making it applicable for all frequencies. S-parameters are popular simply because they are easier to measure in real life. The point is that S-parameter is a great modeling tool for linear circuits, and we should start utilizing it more.

Passing around *.snp files

The idea then is to have a new routine testbench that extracts the n-port model of our own or load circuits. The simulation is as simple as AC analysis, but provides the entire frequency dependent impedance information.

Most simulators have S-parameter analysis (some just as a special case of AC analysis). The interface between designers then becomes “.s2p” files, which could also have best-case/worst-case variants under different PVT conditions. Simulation time remains fast but accuracy improves dramatically. It serves as the perfect balance between using an ideal capacitor and using the extracted netlist of the next block.

In fact, your DUT can also be modelled as a .s3p, .s4p, etc. as long as we are most interested in the circuit’s linear behavior. The same S-parameter files are equally usable in specialized system modelling tools like MATLAB. Modeling active circuits with S-parameter is not something new, but a wheel definitely worth reinventing (check out this 1970 thesis after a simple search).

Limitations of S-parameter models

As you might have guessed, the key limitation to this S-parameter modeling approach is the linear circuit assumption. When nonlinear effects become important (e.g. input amplitude dependent impedance change), small-signal S-parameters could yield different results (but still much better than an ideal capacitor). While there exists a so-called Large-Signal S-Parameter analysis (LSSP), it falls under harmonic balance (HB) or periodic steady state (PSS) analysis, which means it truly focuses more on RF applications. In addition, S-parameters might be limiting when dealing with mixed-signal processing, like sampling circuits.

Nevertheless, I have found impedance/circuit modeling using S-parameters generally allow fast simulation time, better accuracy and less system level frustration down the line. In fact, Analog designers could also gain system insights when interfacing blocks through S-parameters. Give it a try!

Let’s take a small break

System thinking in analog design is a skill that is increasingly more important. Long gone are the days for building “general purpose” devices, and a good system solution require tailored circuits for each application.

First and foremost, we should understand our circuits are processing and their interfaces. I hope the examples discussed in this post open the door for some aspiring analog designers for adopting system mentalities. In the next post, we will move from the interface to the inside of each block, and talk about perhaps the most important architectural tool for analog designers – feedback. Till next time!

Like most fields, circuit design requires a great deal of “learning on the job”. My first encounters with dummies and decoupling capacitors (decaps) were through internships. In fact, they could be the difference makers in a successful tape-out (analog and digital alike). In this post, we will take a deep dive and discuss the best ways to manage these unsung heroes in schematics.

Smart use of dummies

As the name suggests, dummies are devices that are sitting in your designs doing nothing functionally and looking “dumb”. The use of dummies fall under the category of “Design For Manufacturability” or DFM. They ensure that the real operating devices behave as closely to the simulation models as possible. Below are the three main reasons to include dummies

1. Reduce layout dependent effects (LDE) for best device characteristics

The biggest two LDEs are well proximity and length of diffusion effects illustrated below. Basically, all FETs like to think they are the center of the universe. The right thing to do is sacrificing the self-esteem of some dummies to extend the well edge and diffusion length. This is also why multi-finger devices are preferred over single-finger devices despite having the same W/L.

Every process node’s LDE is different, but a general rule of thumb is to add 1-2um worth of dummies on either side for a peace of mind (L0 in the graph above where Vt plateaus). So before starting your design, study the DFM recommendations or even better, draw some devices and simulate.

2. Identical device environments for matching

Even when diffusions can’t be shared (for example, compact logic gates or self-heating limitations), dummies are still necessary to ensure device matching. This also applies to other elements like resistors and capacitors. Specifically, the devices of interest should have the same environments, even including metallization. Below are some examples of where to use dummies for device matching

It’s not easy to share diffusion for single finger inverters without adding extra parasitic loading like in (a). Dummy inverters can be added on both sides to ensure at least the diffusion edges see another diffusion edge consistently. Similar principles apply to resistors in a ladder, matching current sources or MOM fingers in DACs. The idea is to create a regular layout pattern and the active cells are in the middle of said pattern.

3. Spare devices for easier late-stage design tweaks

Preparing for last minute design changes is crucial for any projects. The worst kind of change is for device size because FEOL space is precious and who knows what new DRCs these changes can trigger. There is a whole industry created around ECOs (Engineering Change Order) to handle late-stage design changes, especially for large VLSI systems. By placing dummies (or spare cells) strategically, only metal changes might be necessary for late design changes. My favorite example is the dummy buffers for custom digital timing fixes shown below.

Take a simple timing interface, and let’s say it’s setup time critical in this case in a high-speed custom digital path. The clock path needs some extra delay to give the flip flop sufficient setup margin. We won’t know whether the margin is enough or not until we do post layout simulation. A good practice is to put down some extra buffer/inverter cells, tied as dummies for post layout modifications. Of course, it requires some experience to spot where these spare cells are needed, so start practicing as soon as possible.

Another quick example is putting spare gates for low speed combinatorial logic for fixes late in or even after tape-outs. You might have heard people put NAND and NOR spare gates everywhere for this reason. One tip is to use 4-input NAND/NOR, and tie NAND’s input to high and NOR’s input to low as dummy . This way, they can still be used as 2- or 3-input gates functionally. Modern synthesis and digital flows already automate this, but analog/mixed-signal designers need to be aware of this as well.

This idea also applies to analog circuits. Take the dummies that might exist in a CML circuit: bias current dummies, differential pair dummies and resistor load dummies. They are all available as spares for last minute tweaks in order to squeeze out extra gain or bandwidth. The key here is to reserve the real estate so that only metal changes are necessary. Most layout engineers I worked with are magicians when it comes to quick metal fixes.

The catalog for decaps

There is no such thing as a pure capacitor outside of the mathematics land. That is why you probably have run into pictures like below at some point (a simple tutorial here). The effective series inductance/resistance (ESL/ESR) of a capacitor suppresses its high frequency bypass capability. Even worse, a capacitor can really behave inductively at high enough frequency.

This picture continues on chip. The PCB capacitors rely on in-package or on-die decaps to further suppress the supply impedance rise at higher frequencies. However, on-chip decaps face their own unique challenges, like ESD, leakage, lower quality factor, etc. Let’s first detail out the possible decap choices.

1. PMOS/NMOS gate decap

This is probably the first thing that comes to our minds. We will connect the gate of a PMOS/NMOS to supply/ground, and connect the source and drain to the other. Typically the supply voltage is much larger than the device Vt, so we will get a linear enough decap. To build a high-Q cap, the gate length is typically quite long for smaller gate resistance. However, the overall ESR is still considerable when taking all layers of VIAs and metals into account. Nevertheless, these decaps have much higher capacitance density.

So are we done? Not quite. The biggest issues for these decaps lie in reliability, specially ESD and leakage performance. For many deep sub-micron nodes, the oxide is thin enough for electrons to tunnel through, leading to gate leakage current. For the same reason, the oxide layer is susceptible to breakdown when high voltage is present or an ESD event happens. As a result, these decaps can lead to catastrophic failures if not taken care of. For example, if a positive ESD event happens on the supply, which directly connects to the NMOS’s gate, the device would likely break down, causing huge leakage current or even collapsing the supply.

Between the two flavors, PMOS tend to be the more reliable (not necessarily the better performance) decap choice for most small geometry processes. Planar PMOS has lower gate leakage than NMOS. The parasitic diodes between the Nwell and substrate provide some extra ESD protection. The extra parasitic capacitance between the Nwell and substrate is another point in PMOS’ favor.

2. Cross-coupled decap

To further improve on-chip decaps’ reliability, a cross-coupled decap structure came onto the scene(here is a nice paper on decaps). The structure does look funny – a positive feedback loop leads to a stable biasing point in this decap. Under this operating point, the circuit behaves as two parallel device capacitors, each with a device on-resistance in series. This ESR is much higher than that of the gate decaps, thus will be less effective for high frequency bypassing. However, the increased gate resistance provides extra protection during an ESD event by limiting the current through the gate oxide. Most decaps in standard cell libraries today use similar structures to tradeoff reliability for performance. After all, nothing matters if your chip has a hole burnt through it.

3. Thin vs. thick oxide

Another way to tradeoff reliability and performance is through the use of thick oxide (TOX) devices. TOX devices have much lower leakage current and are rated for higher voltages, and thus have a better chance of surviving ESD events. The cost, however, is smaller capacitance density (smaller capacitance due to larger distance between gate and channel).

There was an anecdote in my Ph.D. lab that a chip returned with huge off-state currents, and unfortunately nothing worked. The root cause was the large area of thin oxide NMOS decaps, coupled with perhaps improper handling of antenna effects, making the chips dead on arrival. After that incident, “only TOX decaps allowed” was an enforced rule in the group.

Industry and academia environments are certainly different and more rigorous rule checks are available today. Nevertheless, I still make my decap choices carefully because of this horror story.

4. MOM, MIM and power grid

Last but not least, we have the good old metal caps. They typically provide better quality factor, linearity and reliability than device caps, but at much lower cap density. Below is an illustration of the physical structures of MOM and MIM caps

In most cases, a MOM capacitor can be stacked directly on top of a device decap to effectively increase density and quality factor. Roughly 20% cap density improvement is achievable with optimized layout. MIM caps might seem efficient because they sit in between top two layers with better density than MOM caps, but the thin plates’ high resistance is a bummer. I never used MIM caps for supply decoupling because they disrupt power grids and have mediocre performance at high frequencies. However, don’t let my personal preference deter you from trying them out and maybe they are the right fit for you.

One other “freebie” for decaps is the sidewall parasitic capacitances between power straps. Therefore, try to interleave your supply/ground lines whenever possible.

Decoupling signals

Let’s get this out of the way first: your supply is a signal. Sadly, not many people realize this until supply noise becomes a problem. What it really means is that a supply or ground pin in schematics is not a small-signal ground, so connecting decaps to these nodes requires some thoughts.

Let’s take a PMOS current bias voltage for instance. Normally a low pass filter exists between the current mirror and the destination current source (either C or RC) to lower noise. The question now is which decap type should we use.

First of all, since the decaps see a finite impedance to supply/ground, ESD is less of a concern (i.e. use of NMOS gate caps is OK). We probably want the highest cap density for area saving, so let’s stack as much MOM capacitors as possible. Ground is typically “quieter”, so let’s bypass to ground. Thus, here is our first attempt:

At first glance, there is nothing wrong with this considering noise sources from Iref or the diode connected PMOS. However, as soon as we think about noise from the supply (which we believed is noisier than ground), it sees a common gate amplifier on the right side at high frequency! If this bias current goes to an oscillator, boy would we have some jitter problems. The correct connection is to bypass the bias voltage to supply, stabilizing Vgs across the PMOS device. At the same time, a PMOS gate cap would be the better choice in terms of layout.

Decoupling signals is often not as straightforward as it seems. I have dealt with signals that needed to have specific ratio of decoupling to supply and ground for optimal performance. Such exercises become more challenging when area becomes a constraint as well. This might seem obvious to some of you, but I am sure we all have made similar mistakes somewhere along the way. I hope this little snippet could save new designers some troubles.

Managing dummies

Finally, we get to the schematics part after a crash course on dummies and decaps.

You might already know my stance on who should initiate and manage dummies/decaps. I strongly believe designers should own the decisions on usage and placements of these devices. As evidenced above, dummies and decaps directly impact circuit performance, and sometimes determines if we have taped out a resistor or brick. So start thinking about them as soon as a schematic hierarchy is created.

There are mainly two types of transistor dummies: ones that connect to a circuit node and ones connected to supplies. My recommendation is to try your best to draw the first type in schematics as intended in layout. It’s OK to leave the supply connected dummies in a corner if you want to make schematics look cleaner, but definitely create your own floorplan. To illustrate, take the simple diff pair example below. One connects dummies to node isrc explicitly, and the other tucks them away in the corner with net name connections. Many schematics out there contain dummies like the left example. For bigger and flatter schematics, it can quickly become difficult to trace.

The next tip involves aligning dummies in the same row as the active devices to reflect layout. The diff pair example didn’t follow this because it’s a simple circuit. We will use a conventional StrongARM latch as an example for this point.

Note that the dummies on the vx nodes remain part of the active schematic similar to the diff pair example. On the right is a boxed section for supply connected dummies put into rows. This might seem redundant since all NMOS devices could be combined, but it creates a template for layout engineers and highlights the relative dummy locations. The dummy sizes DON’T need to be accurate when the schematic is first created. They serve as placeholders for either layout or you to fill in later. Again, dummies are for LDEs, so always keep layout in mind.

If you haven’t already realized, some PMOS dummies on the top row are connected as decaps. In general, don’t waste opportunities to turn dummies into decaps (for supply or bias alike) right next to your circuits. They are the first line of defense against switching currents or capacitive feedthroughs like in a dynamic comparator.

Should we create dedicated dummy wrapper cells? My cop out answer is that it’s a personal choice. However, if you designed the schematic hierarchy right, no level should have enough dummies to even consider a wrapper cell. So my real answer is if a wrapper cell is ever needed, it could just mean your schematic is too flat. Start wrapping active and dummy devices together.

Managing decaps

Most teams probably already have reusable decap cells. If you don’t have them, make them now!

For my first Ph.D. tapeout, the unit decap cell was the biggest time saver towards the end of the project. By using mosaic instantiation, the empty areas around the core circuits were filled up in no time. My first chip didn’t work for other reasons, but I was very proud of the decaps I taped out (can you hear me choking up?).

There could be many details that go into making these reusable decaps. Schematic-wise, they are a collection of unit decap cells with different flavors pulled from the catalog. In modern CMOS designs, these decaps’ unit area in layout fits within a power or standard cell grid. The standard cell decaps are excellent examples. We now just take that concept and apply it to higher level custom decaps.

The first advice might sound silly: make reasonably small symbols for unit decap cells. Decaps are important, but they are not the star of the show. Therefore, the real estate they take up in a schematic sheet should still be small. Case in point: a decap cell symbol in a standard library most likely is smaller than an inverter symbol. Along the same line of thinking, your custom decap cell’s symbol could be slightly bigger to include information about the decap type, but not that much bigger.

Below are some example custom decap symbols, comparing to the sizes of a typical standard cell decap and MOS symbols. By making them small but still informative, tucking these decaps away in a corner makes them less distracting in schematics.

Moving up the schematic hierarchy, different decaps types are necessary for multiple supplies. For example, use thick oxide for IO voltage, combination of thin and thick oxide for core voltage, etc. The advice here is to ALWAYS make a dedicated wrapper cell for all the higher level decaps. The example below is not really drawn to scale. One can imagine the decap wrapper cell symbol being significantly smaller than the rest of the core circuits. Key is to again put the cell away in a corner, but it’s still easily accessible.

So what’s the big deal? Aside from a more modular schematic, there are two other main benefits.

1. This creates a clean interface between design and layout engineers. The layout engineer can update the decap count inside the wrapper cell him/herself without interfering with ongoing changes in the core circuits. This will save everyone some efforts during crunch time.
2. The magic of black boxing makes this schematic more simulatable. Accompanying the decaps are millions of parasitic capacitance and resistance when fully extracted. That’s one of the reasons why post-extraction simulations for higher level schematics are almost impossible. With this schematic, we can mix and match the extraction outputs for all blocks. The decap wrapper can stay in schematic or use C-only extraction. The opposite case could be to have the core circuit stay in schematic, but with a full RC extraction on the decaps and power grids.

The decap wrapper cell doesn’t have to be only on the top most level. In fact, I would recommend putting these cells starting at almost all mid-level blocks. Once you become used to it, it just becomes a habit of copy/paste.

Conclusions

Dummies and decaps are not the sexiest things to talk about (I have tried very hard here). They are nevertheless the key elements that ensure our circuits operate as intended. Here is a quote about decaps by Kent Lundberg (my circuit and feedback class instructor during undergrad): “Decoupling capacitors are like seat belts. You have to use them every time, whether you think you’re going to need them or not.” The same applies to dummies in today’s process nodes.

Subjects like dummies and decaps are often learned on the job or from expensive mistakes. There are many other “boring” but critical elements that require more of our attentions in a design process (mostly DFM related). Often times, fresh grads are overwhelmed with new terminologies, methodologies and productization concepts that weren’t taught in school. To address this, rating the correct usage of dummies/decaps and overall schematics for a class project might be a good starting point .

Mistakes in chip design are expensive. Ironically, the hard truth is that sometimes people learn best from expensive mistakes. The best tradeoff, then, might be to share and openly discuss more “horror stories” in order to save younger designers from these million-dollar downfalls.