Draw It Like You See It – Schematic and Layout Duality

The verdict is final: layout IS the design. The images below taken from Alvin Loke’s CICC slides (watch his recent talk here) summarize the key challenges in modern CMOS designs. Layout effort grows linearly (I think it’s more than that) due to more stringent DRC rules and longer design iterations. As a result, it has forced changes on most of our design mentality (although we designers are a stubborn breed). I began to re-evaluate the way I draw schematics because I know eventually a good layout is king. I still hold the personal belief that it’s more likely to work if it looks good. This applies to both schematics and layout.

Design in reverse

I was fortunate enough to have early access to finFET processes (16nm to be exact) during my Ph.D years. Funny story: when I first stared at a finFET layout, I assumed all gates are shorted due to the continuous poly lines. You can imagine my facial expressions when I learned about poly and MD cuts (😲+ 🤬 + 😭). It took me about 3-4 circuit blocks to fully understand the “evil” that is parasitics in finFETs. The LVS ignorable parasitic caps that double your circuit’s power seem innocent next to the parasitic resistors that smirk at you as they make your netlist size explode. Eventually, I decided to do my designs in reverse: never begin schematics/simulations before layout placement. It might sound counter intuitive, but here are the biggest reasons and benefits for adopting this methodology

1. Save time for everyone in the design cycle
   Think in the shoes of layout engineers. They need to tell you that your circuit is impossible to draw due to some DRC. They probably spent a whole day trying to figure this out, but this bad news seemed inevitable. Frustrations and tension fill the room. These scenarios could be avoided if the designers already understood the floorplan/DRC limitations. So instead of “optimizing” the circuits only in SPICE land, start with layout.
2. Layout can determine your sizing, not simulations
   Designers tend to “overdesign” a cell when assigned a small puzzle piece in a big block. We run hundreds of simulations to squeeze out that 0.1dB extra performance, only to find out later that there is no difference with post layout extractions. Nature is kind to us: we often deal with shallow optima and a single transistor’s size wouldn’t matter too much in the grand scheme of things. So instead of running tons of simulations, your design choice might be informed by what works better in layout. One example would be increasing a device’s finger by one would help reduce the cell’s width due to abutment.
3. Begin thinking about creating hierarchies because of layout “tediousness”
   A good schematics hierarchy could also help increase layout’s efficiency. To fully understand the importance of good hierarchical schematics, you need to experience the painful repetitive tasks in layout firsthand.
4. Embed your design intent for parasitics into the floorplan
   No matter how good your cartoon floorplans in schematics are, it doesn’t come close to real layout floorplans. You might gain new insights after just laying down your tiny transistors and some wires. You might also want to break the OD diffusion to squeeze in more contacts. So, you change an NMOS from a single 10 finger device to 10x single finger devices. You can then draw schematics with design intents for parasitics, but you need to OWN the layout floorplan for that to happen.

The design/layout Venn diagram

I have this mental Venn diagram for design and layout. I remind our team’s designers that a majority of their design efforts should be in layout, with awareness of floorplan, DRC and parasitics at a minimum. On the other hand, a good layout engineer should be an electrical engineer at heart, knowing when to tradeoff parasitic capacitors and resistors, capable of suggesting better floorplans, and just a wizard with those hot keys.

It is certainly easier said than done, and I believe designers should take the initiative to reach across the aisle. DO NOT think you are doing layout engineers’ job, but rather you are helping yourself down the line. I promise you that your design’s “time to completion” will reduce significantly. Everyone in the layout team will shower you with appreciation if you are just a little more layout savvy.

Layout-like schematics

Enough of my ranting about how designers should learn layout, let’s discuss how at least we can draw schematics with layout in mind.

Different companies have different ways of managing their schematics at various levels. For large SoC companies, there might be a transition from a more manual and analog way of managing schematics to more digital like methodologies (i.e. netlist, Verilog, etc.) somewhere in the hierarchy. In these cases, the higher level schematics are mostly auto generated and human unreadable. Sometimes this makes sense because the chip becomes just a combination of macros and functional verifications can be more efficient with the help of digital tools. Nevertheless, drawing good schematics that reflect layout is still a good idea at mid/low level. It is really a personal choice deciding at which level or for which cell to draw a layout-like schematic, but it is a practice that could fit any hierarchy level.

It’s time to get our hands dirty. The biggest hurdle we need to jump over first is the default rectangle symbol shapes handed to us by the EDA tools. Its partner in crime is the selection box, the invisible border that defines the symbol boundary and limits your creativity. The conventional wisdom says input on the left and outputs on the right. We have been going with the flow for a while, and to be fair, they certainly get the job done. To break from this convention, here is the corner selection box that allows you to draw symbols with any shape.

This allows you to create very layout like symbols, yet provide a clear entry point to descent down. To illustrate, below is a top level schematic with a pad ring. The boring rectangle symbols will result in a schematics that look like this (I didn’t put all the pin names on there for simplicity)

Now if I draw the pad ring symbol as a real ring with the corner selection box, the schematics can turn into something like below

Let’s detail out the ways why this is better

• The pad locations are explicit, so you can get a lot of information from schematics alone. You can already visualize signal/current flows. You know exactly how many and where the spare pads are just in case. You know how to floorplan internal block’s I/O pins. The list goes on.
• It makes more sense to have duplicate pins on this pad ring symbol because it reflects the physical layout. Thus, you have an immediate idea of how many pads are available for the same signals, especially important for supply/ground.
• Although I didn’t draw it here, you can imagine how one can expand this symbol to annotate each pad type (e.g. ESD strength, I/O pad type, etc.), adopting the schematics as documentation principle.
• The sense of pride that comes with drawing and admiring this finished schematic, which you treasure almost as much as your kids (ok, maybe not that much).

Another dummy example

Now let’s move to a lower level dummy block for another example. I want to emphasize that this is not a real design and probably doesn’t even work. However, it’s a great example to show how to draw layout-like schematics. Take a digital LDO (since we did an analog one before) and we will focus on the custom digital controller and the PMOS array. Below shows the block diagram

As you can see, this block diagram serves as a pseudo floorplan for the layout as well. I will show you the final schematics first, and go into each sub-block respectively.

We will dive into the PMOS array (or more precisely matrix) first. This cell embodies the notion that the layout is the design. It’s quite straightforward schematic wise but the nuances are all in layout. My preferred way to draw this cell for layout is to create row and column hierarchies like below

Note that I purposedly make the csel bus come from the bottom to match the layout. The vin/vout pin directions are more conventional since there is no easy way to indicate a 3D structure (i.e. VIA up and down) in schematics.

Those eagle-eyed among you may already see that the schematics can be more simplified and scaling friendly using bus notations. When the matrix size is large (e.g. >256 elements or 8 bits), the bus notation makes sense. Otherwise, I think 16 rows + 16 cols can still be drawn out explicitly to reflect layout (that’s roughly 2log2(16) = 8 Ctrl C+V operations, so not that bad). Together with a cartoon floorplan and more notes in the schematics, you can confidently hand this off to your layout partner.

Now we will move onto the custom digital block. The more interesting subcell here is the shift register, so I will expand on it further. For the digital block itself, you can clearly see the three subcells and their relative position w.r.t each other. They can be placed into an L-shape with standard cells, fillers and decaps, just like in the schematics. Of course I didn’t forget to draw a note box to indicate the higher level connections to the PMOS matrix. One benefit with this style of schematics (which might not be obvious until you try it yourself) is you rarely have to connect by net names because the signal directions are preserved like in the layout.

If we descend into the shift register cell, I would draw something like the following. The example design intent here is to run the clock signal against the data path to lower the hold time violation risk. Thus the data input needs to be buffered to the other side of the register chain. The extra buffer delay will act as hold time margin for the first DFF.

Note that I also space out the data buffers and annotate the approximate distance between them. The data buffer size is already chosen appropriately because I know the metal usage and wire length in advance. The clock signal also has the same annotations along with a note symbol for shielding. It’s all possible because I have played around with layout floorplan before drawing this schematic. Again, we can simplify this schematic before the shift register gets too long. It might lose some layout information, so you can add a cartoon floorplan in the corner as a supplement.

Final points

In the interest of keeping this post at reasonable length, I won’t include any more specific examples. However, here is a list for layout information that can be explicitly shown in schematics

1. Routing path features including 45/90 degree turns and branching for critical signals, especially if distributed long distance (e.g. clocks).
2. Directionality between critical signals (e.g. show if data and clock paths are parallel or orthogonal).
3. Special routing plans like a tree structure for matching or star connection for power.
4. Inductor coil placements relative to other cells.
5. Higher level block symmetry (for instance, replicated I/Q mixer in a RF signal path).
6. Common centroid placements and connections for first order gradient cancellation (differential pairs, binary/segmented DACs, etc.).
7. The list can go on as you start to draw it like you see it…

As a closing thought, I started this post with a focus on modern CMOS and finFET, but the principles of design in reverse and drawing layout-like schematics is equally suitable for older process technologies. Designers have to evolve and understand bottlenecks and constraints often lie in other aspects, especially layout. By the same token, I also encourage designers to learn about new ideas in signal processing and systems.

In an ideal world, the Venn diagram described above would have a third circle for system design. Work flows and available talents nowadays force most teams to operate like the diagram on the left. Each circle will expand over time thanks to new technology and tools, but it’s the right overlaps that push innovation forward and ensure execution. We should all aspire to be in the middle of the intersections, and younger generation engineers should be trained as such. So gauge yourself against this picture, and move towards the center 1dB each day and one day at a time.